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Author	SHA1	Message	Date
柚木 鉉	28ff8bb8f7	catch SIGSEGV in sig caught (#119) ... In the RISC-V extension instruction set, there are cases where cores from different manufacturers and different functional extension instructions share the same op. In such situations, it is necessary to add SIGSEGV handling to prevent program termination.	2024-07-27 14:14:42 +08:00
柚木 鉉	b42485d56e	add vlang binding (#67)	2024-03-02 10:52:39 +08:00
柚木 鉉	2008665a13	ruapu SyterKit v0.2.6.1 support (#56)	2024-03-01 20:41:44 +08:00
柚木 鉉	335ce5fa60	detect openrisc core, support orbis32, orbis64, orfpx32, orfpx64, orvdx64 (#43)	2024-02-25 20:36:51 +08:00