detect rvv1.0 and its extensions (#107)
* detect rvv1.0 and its extensions * use vaaddu to detect v extension * Use `csrr a0, vlenb` for VLEN probe * check if vcsr is available first * inline helper functions into their callers
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Yingwei Zheng
GitHub
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@ -69,7 +69,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
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|powerpc|`vsx`|
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|s390x|`zvector`|
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|loongarch|`lsx` `lasx`|
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|risc-v|`i` `m` `a` `f` `d` `c` `zba` `zbb` `zbc` `zbs` `zbkb` `zbkc` `zbkx` `zfa` `zfbfmin` `zfh` `zfhmin` `zicond` `zicsr` `zifencei` `zmmul` `xtheadba` `xtheadbb` `xtheadbs` `xtheadcondmov` `xtheadfmemidx` `xtheadfmv` `xtheadmac` `xtheadmemidx` `xtheadmempair` `xtheadsync` `xtheadvdot`|
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|risc-v|`i` `m` `a` `f` `d` `c` `v` `zba` `zbb` `zbc` `zbs` `zbkb` `zbkc` `zbkx` `zfa` `zfbfmin` `zfh` `zfhmin` `zicond` `zicsr` `zifencei` `zmmul` `zvbb` `zvbc` `zvfh` `zvfhmin` `zvfbfmin` `zvfbfwma` `zvkb` `zvl32b` `zvl64b` `zvl128b` `zvl256b` `zvl512b` `zvl1024b` `xtheadba` `xtheadbb` `xtheadbs` `xtheadcondmov` `xtheadfmemidx` `xtheadfmv` `xtheadmac` `xtheadmemidx` `xtheadmempair` `xtheadsync` `xtheadvdot`|
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|openrisc| `orbis32` `orbis64` `orfpx32` `orfpx64` `orvdx64` |
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## Let's ruapu
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14
main.c
14
main.c
@ -127,6 +127,7 @@ int main()
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PRINT_ISA_SUPPORT(f)
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PRINT_ISA_SUPPORT(d)
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PRINT_ISA_SUPPORT(c)
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PRINT_ISA_SUPPORT(v)
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PRINT_ISA_SUPPORT(zba)
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PRINT_ISA_SUPPORT(zbb)
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PRINT_ISA_SUPPORT(zbc)
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@ -142,6 +143,19 @@ int main()
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PRINT_ISA_SUPPORT(zicsr)
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PRINT_ISA_SUPPORT(zifencei)
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PRINT_ISA_SUPPORT(zmmul)
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PRINT_ISA_SUPPORT(zvbb)
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PRINT_ISA_SUPPORT(zvbc)
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PRINT_ISA_SUPPORT(zvfh)
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PRINT_ISA_SUPPORT(zvfhmin)
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PRINT_ISA_SUPPORT(zvfbfmin)
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PRINT_ISA_SUPPORT(zvfbfwma)
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PRINT_ISA_SUPPORT(zvkb)
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PRINT_ISA_SUPPORT(zvl32b)
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PRINT_ISA_SUPPORT(zvl64b)
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PRINT_ISA_SUPPORT(zvl128b)
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PRINT_ISA_SUPPORT(zvl256b)
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PRINT_ISA_SUPPORT(zvl512b)
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PRINT_ISA_SUPPORT(zvl1024b)
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PRINT_ISA_SUPPORT(xtheadba)
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PRINT_ISA_SUPPORT(xtheadbb)
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57
ruapu.h
57
ruapu.h
@ -19,6 +19,7 @@ const char* const* ruapu_rua();
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#ifdef RUAPU_IMPLEMENTATION
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#include <stdint.h>
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#include <string.h>
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typedef void (*ruapu_some_inst)();
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@ -334,6 +335,48 @@ RUAPU_INSTCODE(xtheadmempair, 0xe0a1450b) // th.lwd a0,a0,(sp),#0,3
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RUAPU_INSTCODE(xtheadsync, 0x0180000b) // th.sync
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RUAPU_INSTCODE(xtheadvdot, 0x8000600b) // th.vmaqa.vv v0,v0,v0
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// RVV 1.0 support
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// unimp (csrrw x0, cycle, x0)
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#define RUAPU_RV_TRAP() asm volatile(".align 2\n.word 0xc0001073")
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// vcsr is only defined in rvv 1.0, which doesn't exist in rvv 0.7.1 or xtheadvector.
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// csrr x0, vcsr
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#define RUAPU_RVV1P0_AVAIL() asm volatile(".align 2\n.word 0x00f02573")
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// csrr res, vlenb
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#define RUAPU_DETECT_ZVL(len) static void ruapu_some_zvl##len##b() { \
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RUAPU_RVV1P0_AVAIL(); \
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intptr_t res; \
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asm volatile(".align 2\n.insn i 0x73, 0x2, %0, x0, -990" : "=r"(res)); \
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if (res < len/8) RUAPU_RV_TRAP(); \
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}
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RUAPU_DETECT_ZVL(32)
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RUAPU_DETECT_ZVL(64)
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RUAPU_DETECT_ZVL(128)
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RUAPU_DETECT_ZVL(256)
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RUAPU_DETECT_ZVL(512)
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RUAPU_DETECT_ZVL(1024)
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#undef RUAPU_DETECT_ZVL
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// vsetvl res, zero, vtype
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// check vill bits after vsetvl
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#define RUAPU_RVV_INSTCODE(isa, vtype, ...) static void ruapu_some_##isa() { \
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RUAPU_RVV1P0_AVAIL(); \
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intptr_t res; \
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asm volatile(".align 2\n.insn r 0x57, 0x7, 0x40, %0, x0, %1" : "=r"(res) : "r"(vtype)); \
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if (res < 0) RUAPU_RV_TRAP(); \
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asm volatile(".align 2\n.word " #__VA_ARGS__ ); \
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}
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RUAPU_RVV_INSTCODE(zvbb, 0, 0x4a862257) // vclz.v v4, v8 with SEW = 8
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RUAPU_RVV_INSTCODE(zvbc, 0, 0x32842257) // vclmul.vv v4, v8, v8 with SEW = 8
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RUAPU_RVV_INSTCODE(zvfh, 8, 0x02841257) // vfadd.vv v4, v8, v8 with SEW = 16
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RUAPU_RVV_INSTCODE(zvfhmin, 8, 0x4a8a1257) // vfncvt.f.f.v v4, v8 with SEW = 16
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RUAPU_RVV_INSTCODE(zvfbfmin, 8, 0x4a8e9257) // vfncvtbf16.f.f.w v4, v8 with SEW = 16
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RUAPU_RVV_INSTCODE(zvfbfwma, 8, 0xee855257) // vfwmaccbf16.vf v4, fa0, v8 with SEW = 16
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RUAPU_RVV_INSTCODE(zvkb, 0, 0x56860257) // vrol.vv v4, v8, v12 with SEW = 8
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RUAPU_RVV_INSTCODE(v, 24, 0x22842257) // vaaddu.vv v4, v8, v8 with SEW = 64
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#undef RUAPU_RVV_INSTCODE
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#undef RUAPU_RV_TRAP
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#undef RUAPU_RVV1P0_AVAIL
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#endif
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#undef RUAPU_INSTCODE
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@ -461,6 +504,7 @@ RUAPU_ISAENTRY(a)
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RUAPU_ISAENTRY(f)
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RUAPU_ISAENTRY(d)
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RUAPU_ISAENTRY(c)
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RUAPU_ISAENTRY(v)
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RUAPU_ISAENTRY(zba)
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RUAPU_ISAENTRY(zbb)
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RUAPU_ISAENTRY(zbc)
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@ -476,6 +520,19 @@ RUAPU_ISAENTRY(zicond)
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RUAPU_ISAENTRY(zicsr)
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RUAPU_ISAENTRY(zifencei)
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RUAPU_ISAENTRY(zmmul)
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RUAPU_ISAENTRY(zvbb)
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RUAPU_ISAENTRY(zvbc)
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RUAPU_ISAENTRY(zvfh)
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RUAPU_ISAENTRY(zvfhmin)
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RUAPU_ISAENTRY(zvfbfmin)
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RUAPU_ISAENTRY(zvfbfwma)
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RUAPU_ISAENTRY(zvkb)
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RUAPU_ISAENTRY(zvl32b)
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RUAPU_ISAENTRY(zvl64b)
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RUAPU_ISAENTRY(zvl128b)
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RUAPU_ISAENTRY(zvl256b)
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RUAPU_ISAENTRY(zvl512b)
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RUAPU_ISAENTRY(zvl1024b)
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RUAPU_ISAENTRY(xtheadba)
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RUAPU_ISAENTRY(xtheadbb)
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