loongarch support (#30)
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@ -6,7 +6,7 @@
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Detect CPU ISA features with single-file
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Detect CPU ISA features with single-file
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<table>
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<table>
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<tr><td>CPU</td><td>✅ x86, x86-64<br/>✅ arm, aarch64<br/>✅ mips<br/>✅ powerpc<br/>✅ s390x<br/>✅ risc-v</td><td rowspan=3>
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<tr><td>CPU</td><td>✅ x86, x86-64<br/>✅ arm, aarch64<br/>✅ mips<br/>✅ powerpc<br/>✅ s390x<br/>✅ risc-v<br/>✅ loongarch</td><td rowspan=3>
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```c
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```c
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#define RUAPU_IMPLEMENTATION
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#define RUAPU_IMPLEMENTATION
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@ -223,7 +223,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
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|mips|`msa`|
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|mips|`msa`|
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|powerpc|`vsx`|
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|powerpc|`vsx`|
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|s390x|`zvector`|
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|s390x|`zvector`|
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|loongarch||
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|loongarch|`lsx` `lasx`|
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|risc-v|`i` `m` `a` `f` `d` `c`|
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|risc-v|`i` `m` `a` `f` `d` `c`|
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## Techniques inside ruapu
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## Techniques inside ruapu
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4
main.c
4
main.c
@ -87,6 +87,10 @@ int main()
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PRINT_ISA_SUPPORT(d)
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PRINT_ISA_SUPPORT(d)
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PRINT_ISA_SUPPORT(c)
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PRINT_ISA_SUPPORT(c)
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#elif __loongarch__
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PRINT_ISA_SUPPORT(lsx)
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PRINT_ISA_SUPPORT(lasx)
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#endif
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#endif
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return 0;
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return 0;
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10
ruapu.h
10
ruapu.h
@ -136,7 +136,7 @@ static int ruapu_detect_isa(ruapu_some_inst some_inst)
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#if defined(__i386__) || defined(__x86_64__) || __s390x__
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#if defined(__i386__) || defined(__x86_64__) || __s390x__
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".byte " #__VA_ARGS__ : : : ); }
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".byte " #__VA_ARGS__ : : : ); }
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#elif __aarch64__ || __arm__ || __mips__ || __riscv
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#elif __aarch64__ || __arm__ || __mips__ || __riscv || __loongarch__
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".word " #__VA_ARGS__ : : : ); }
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".word " #__VA_ARGS__ : : : ); }
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#elif __powerpc__
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#elif __powerpc__
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".long " #__VA_ARGS__ : : : ); }
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#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".long " #__VA_ARGS__ : : : ); }
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@ -240,6 +240,10 @@ RUAPU_INSTCODE(f, 0x10a57553) // fmul.s fa0,fa0,fa0
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RUAPU_INSTCODE(d, 0x12a57553) // fmul.d fa0,fa0,fa0
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RUAPU_INSTCODE(d, 0x12a57553) // fmul.d fa0,fa0,fa0
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RUAPU_INSTCODE(c, 0x0001952a) // add a0,a0,a0 + nop
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RUAPU_INSTCODE(c, 0x0001952a) // add a0,a0,a0 + nop
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#elif __loongarch__
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RUAPU_INSTCODE(lsx, 0x700b0000) //vadd.w vr0, vr0, vr0
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RUAPU_INSTCODE(lasx, 0x740b0000) //xvadd.w xr0, xr0, xr0
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#endif
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#endif
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#undef RUAPU_INSTCODE
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#undef RUAPU_INSTCODE
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@ -320,6 +324,10 @@ RUAPU_ISAENTRY(f)
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RUAPU_ISAENTRY(d)
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RUAPU_ISAENTRY(d)
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RUAPU_ISAENTRY(c)
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RUAPU_ISAENTRY(c)
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#elif __loongarch__
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RUAPU_ISAENTRY(lsx)
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RUAPU_ISAENTRY(lasx)
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#endif
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#endif
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};
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};
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