From 991d5aacf8d50b4ed216db98d612f5d968cdaa8b Mon Sep 17 00:00:00 2001
From: nihui <shuizhuyuanluo@126.com>
Date: Sun, 25 Feb 2024 16:23:12 +0800
Subject: [PATCH] detect more aarch64 crypto extensions

---
 README.md |  2 +-
 main.c    |  5 +++++
 ruapu.h   | 10 ++++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index ebb44d5..aee2b20 100644
--- a/README.md
+++ b/README.md
@@ -255,7 +255,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
 |:---:|---|
 |x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avxvnni` `avxvnniint8` `avxifma`|
 |arm|`edsp` `neon` `vfpv4` `idiv`|
-|aarch64|`neon` `vfpv4` `cpuid` `asimdrdm` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `mte` `sve` `sve2` `svebf16` `svei8mm` `svef32mm` `sha3` `sha512` `sm3` `sm4` `amx`|
+|aarch64|`neon` `vfpv4` `cpuid` `asimdrdm` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `mte` `sve` `sve2` `svebf16` `svei8mm` `svef32mm` `pmull` `crc32` `aes` `sha1` `sha2` `sha3` `sha512` `sm3` `sm4` `amx`|
 |mips|`msa`|
 |powerpc|`vsx`|
 |s390x|`zvector`|
diff --git a/main.c b/main.c
index cd929d3..5363a4d 100644
--- a/main.c
+++ b/main.c
@@ -61,6 +61,11 @@ int main()
     PRINT_ISA_SUPPORT(svebf16)
     PRINT_ISA_SUPPORT(svei8mm)
     PRINT_ISA_SUPPORT(svef32mm)
+    PRINT_ISA_SUPPORT(pmull)
+    PRINT_ISA_SUPPORT(crc32)
+    PRINT_ISA_SUPPORT(aes)
+    PRINT_ISA_SUPPORT(sha1)
+    PRINT_ISA_SUPPORT(sha2)
     PRINT_ISA_SUPPORT(sha3)
     PRINT_ISA_SUPPORT(sha512)
     PRINT_ISA_SUPPORT(sm3)
diff --git a/ruapu.h b/ruapu.h
index 8d6da47..59c791b 100644
--- a/ruapu.h
+++ b/ruapu.h
@@ -201,6 +201,11 @@ RUAPU_INSTCODE(sve2, 0x44405000) // smlslb z0.h,z0.b,z0.b
 RUAPU_INSTCODE(svebf16, 0x6460e400) // bfmmla z0.s,z0.h,z0.h
 RUAPU_INSTCODE(svei8mm, 0x45009800) // smmla z0.s,z0.b,z0.b
 RUAPU_INSTCODE(svef32mm, 0x64a0e400) // fmmla z0.s,z0.s,z0.s
+RUAPU_INSTCODE(pmull, 0x0e20e000) // pmull v0.8h,v0.8b,v0.8b
+RUAPU_INSTCODE(crc32, 0x1ac04000) // crc32b w0,w0,w0
+RUAPU_INSTCODE(aes, 0x4e285800) // aesd v0.16b,v0.16b
+RUAPU_INSTCODE(sha1, 0x5e280800) // sha1h s0,s0
+RUAPU_INSTCODE(sha2, 0x5e004000) // sha256h q0,q0,v0.4s
 RUAPU_INSTCODE(sha3, 0xce000000) // eor3 v0.16b, v0.16b, v0.16b, v0.16b
 RUAPU_INSTCODE(sha512, 0xce608000) // sha512h q0, q0, v0.2d
 RUAPU_INSTCODE(sm3, 0xce60c000) // sm3partw1 v0.4s, v0.4s, v0.4s
@@ -309,6 +314,11 @@ RUAPU_ISAENTRY(sve2)
 RUAPU_ISAENTRY(svebf16)
 RUAPU_ISAENTRY(svei8mm)
 RUAPU_ISAENTRY(svef32mm)
+RUAPU_ISAENTRY(pmull)
+RUAPU_ISAENTRY(crc32)
+RUAPU_ISAENTRY(aes)
+RUAPU_ISAENTRY(sha1)
+RUAPU_ISAENTRY(sha2)
 RUAPU_ISAENTRY(sha3)
 RUAPU_ISAENTRY(sha512)
 RUAPU_ISAENTRY(sm3)