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detect openrisc core, support orbis32, orbis64, orfpx32, orfpx64, orvdx64 (#43)

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柚木 鉉 2024-02-25 20:36:51 +08:00 committed by GitHub
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3 changed files with 32 additions and 2 deletions
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3
README.md
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@ -6,7 +6,7 @@
Detect CPU ISA features with single-file Detect CPU ISA features with single-file
<table> <table>
<tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64<br/>&#9989; mips<br/>&#9989; powerpc<br/>&#9989; s390x<br/>&#9989; loongarch<br/>&#9989; risc-v</td><td rowspan=3> <tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64<br/>&#9989; mips<br/>&#9989; powerpc<br/>&#9989; s390x<br/>&#9989; loongarch<br/>&#9989; risc-v<br/>&#9989; openrisc</td><td rowspan=3>
```c ```c
#define RUAPU_IMPLEMENTATION #define RUAPU_IMPLEMENTATION
@ -267,6 +267,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
|s390x|`zvector`| |s390x|`zvector`|
|loongarch|`lsx` `lasx`| |loongarch|`lsx` `lasx`|
|risc-v|`i` `m` `a` `f` `d` `c` `zfa` `zfh` `zfhmin` `zicsr` `zifencei` `zmmul` | |risc-v|`i` `m` `a` `f` `d` `c` `zfa` `zfh` `zfhmin` `zicsr` `zifencei` `zmmul` |
|openrisc| `orbis32` `orbis64` `orfpx32` `orfpx64` `orvdx64` |
## Techniques inside ruapu ## Techniques inside ruapu
ruapu is implemented in C language to ensure the widest possible portability. ruapu is implemented in C language to ensure the widest possible portability.

7
main.c
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@ -104,6 +104,13 @@ int main()
PRINT_ISA_SUPPORT(zicsr) PRINT_ISA_SUPPORT(zicsr)
PRINT_ISA_SUPPORT(zifencei) PRINT_ISA_SUPPORT(zifencei)
#elif __openrisc__
PRINT_ISA_SUPPORT(orbis32)
PRINT_ISA_SUPPORT(orbis64)
PRINT_ISA_SUPPORT(orfpx32)
PRINT_ISA_SUPPORT(orfpx64)
PRINT_ISA_SUPPORT(orvdx64)
#endif #endif
return 0; return 0;

24
ruapu.h
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@ -358,11 +358,31 @@ RUAPU_ISAENTRY(zicsr)
RUAPU_ISAENTRY(zifencei) RUAPU_ISAENTRY(zifencei)
RUAPU_ISAENTRY(zmmul) RUAPU_ISAENTRY(zmmul)
#elif __openrisc__
RUAPU_ISAENTRY(orbis32)
RUAPU_ISAENTRY(orbis64)
RUAPU_ISAENTRY(orfpx32)
RUAPU_ISAENTRY(orfpx64)
RUAPU_ISAENTRY(orvdx64)
#endif #endif
}; };
#undef RUAPU_ISAENTRY #undef RUAPU_ISAENTRY
#if defined __openrisc__
static void ruapu_detect_openrisc_isa()
{
uint32_t value;
uint16_t addr = U(0x0000);
asm volatile ("l.mfspr %0, r0, %1" : "=r" (value) : "K" (addr));
for (size_t i = 0; i < sizeof(g_ruapu_isa_map) / sizeof(g_ruapu_isa_map[0]); i++)
{
g_ruapu_isa_map[0].capable = ((value) >> (5 + i)) & 0x1;
}
}
#endif
void ruapu_init() void ruapu_init()
{ {
#if defined _WIN32 || defined __ANDROID__ || defined __linux__ || defined __APPLE__ || defined __FreeBSD__ || defined __NetBSD__ || defined __OpenBSD__ #if defined _WIN32 || defined __ANDROID__ || defined __linux__ || defined __APPLE__ || defined __FreeBSD__ || defined __NetBSD__ || defined __OpenBSD__
@ -370,7 +390,9 @@ void ruapu_init()
{ {
g_ruapu_isa_map[i].capable = ruapu_detect_isa(g_ruapu_isa_map[i].inst); g_ruapu_isa_map[i].capable = ruapu_detect_isa(g_ruapu_isa_map[i].inst);
} }
#else #elif defined __openrisc__
ruapu_detect_openrisc_isa();
#else
// initialize g_ruapu_isa_map for baremetal here, default all zero // initialize g_ruapu_isa_map for baremetal here, default all zero
// there is still ruapu_some_XYZ() functions available // there is still ruapu_some_XYZ() functions available
// but you have to work out your own signal handling // but you have to work out your own signal handling