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risc-v support (#19)

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nihui 2024-02-22 13:43:43 +08:00 committed by GitHub
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commit 2d3681e101
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3 changed files with 28 additions and 6 deletions
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4
README.md
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@ -6,7 +6,7 @@
Detect CPU ISA features with single-file
<table>
<tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64</td><td rowspan=3>
<tr><td>CPU</td><td>&#9989; x86, x86-64<br/>&#9989; arm, aarch64<br/>&#9989; risc-v</td><td rowspan=3>
```c
#define RUAPU_IMPLEMENTATION
@ -223,7 +223,7 @@ _`fma4` on zen1, ISA in hypervisor, etc._
|mips||
|powerpc||
|loongarch||
|risc-v||
|risc-v|`i` `m` `a` `f` `d` `c`|
## Techniques inside ruapu
ruapu is implemented in C language to ensure the widest possible portability.

8
main.c
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@ -65,6 +65,14 @@ int main()
PRINT_ISA_SUPPORT(neon)
PRINT_ISA_SUPPORT(vfpv4)
#elif __riscv
PRINT_ISA_SUPPORT(i)
PRINT_ISA_SUPPORT(m)
PRINT_ISA_SUPPORT(a)
PRINT_ISA_SUPPORT(f)
PRINT_ISA_SUPPORT(d)
PRINT_ISA_SUPPORT(c)
#endif
return 0;

22
ruapu.h
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@ -130,11 +130,9 @@ static int ruapu_detect_isa(ruapu_some_inst some_inst)
return g_ruapu_sigill_caught ? 0 : 1;
}
#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
#if defined(__i386__) || defined(__x86_64__)
#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".byte " #__VA_ARGS__ : : : ); }
#elif __aarch64__
#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".word " #__VA_ARGS__ : : : ); }
#elif __arm__
#elif __aarch64__ || __arm__ || __riscv
#define RUAPU_INSTCODE(isa, ...) static void ruapu_some_##isa() { asm volatile(".word " #__VA_ARGS__ : : : ); }
#endif
@ -213,6 +211,14 @@ RUAPU_INSTCODE(neon, 0xf2000d40) // vadd.f32 q0,q0,q0
RUAPU_INSTCODE(vfpv4, 0xf3b60600) // vcvt.f16.f32 d0,q0
#endif
#elif __riscv
RUAPU_INSTCODE(i, 0x00a50533) // add a0,a0,a0
RUAPU_INSTCODE(m, 0x02a50533) // mul a0,a0,a0
RUAPU_INSTCODE(a, 0x100122af, 0x185122af) // lr.w t0,(sp) + sc.w t0,t0,(sp)
RUAPU_INSTCODE(f, 0x10a57553) // fmul.s fa0,fa0,fa0
RUAPU_INSTCODE(d, 0x12a57553) // fmul.d fa0,fa0,fa0
RUAPU_INSTCODE(c, 0x0001952a) // add a0,a0,a0 + nop
#endif
#undef RUAPU_INSTCODE
@ -271,6 +277,14 @@ RUAPU_ISAENTRY(edsp)
RUAPU_ISAENTRY(neon)
RUAPU_ISAENTRY(vfpv4)
#elif __riscv
RUAPU_ISAENTRY(i)
RUAPU_ISAENTRY(m)
RUAPU_ISAENTRY(a)
RUAPU_ISAENTRY(f)
RUAPU_ISAENTRY(d)
RUAPU_ISAENTRY(c)
#endif
};